This topic was moved here from #cranelift > F32X8 Type fails lane width assertion on aarch64 by Finn H.
Cranelift generally only has support for 128-bit vectors at this time, 256+ will likely hit bugs like this
At least on x64, platforms like risc-v may fare better but in general 256+ is not tested much and probably won't work
Fair enough. Are there any tracking issues for wider vector support?
Also is there a reason this is enforced with a panicking assert and not returning an Error?
I'm not aware of an issue myself, and I agree it'd be better to have an error than a panic!
I see, i will probably try and open an issue about it then. Thank you for your help @Alex Crichton
Last updated: Feb 27 2025 at 22:03 UTC