Trevor Klingler (Jul 20 2025 at 18:34): Trevor Klingler (Jul 20 2025 at 18:34):TL;DR, I want to create a new instruction set for a custom simulated CPU I made. What are the places I need to insert new code, what pitfalls might I need to be aware of, and what resources are available for help?
As a bit of background, I'm an electrical engineer with a long background of programming, especially Rust as of late. Back in college I made a CPU with a custom instruction set as part of a class, that I then expanded to be "complete". I made a simple python "assembler" of sorts to compile my own assembly into the required machine code, then was able to insert it into the ROM of the CPU to run it. It was overall a fun project (here, in case anyone's curious).
It struck me that it's theoretically possible that I could hijack existing projects, like LLVM or Cranelift, to compile rust code for this CPU, which seems really exciting to me. LLVM has a guide for contributing a new ISA, but I'd rather not pursue that route because writing that much heavy C++ just doesn't excite me. That's when I remembered that Rust supports Cranelift as an experimental backend, and I started taking a look.
I've found a couple places that are obvious candidates to add a new ISA, like cranelift/codegen/src/isa, where I might be able to get away with mostly copy-pasting the RISCV ISA and disecting/modifying it, but I've been unable to find any kind of guidance on doing so, which makes that seem very daunting.
I'd be happy to work through this and write up a guide (maybe a blog post or something) for future contributors so that others have a starting point for creating a new ISA, but before I fully commit to the project, I wanted to get people's impressions here of the feasibility of doing this, and their thoughts on the best way to get started.
This is completely a hobby project, and I work full time and am working through a master's degree, so it's not like I'll get this done overnight or any time soon, but I still think it'd be super fun. I'd appreciate any help anyone's willing to offer, and I especially appreciate your patience. Thanks.
Edit: also, I'm very aware that the simulated CPU will likely need some fairly extensive improvements to work as expected as well, but that's probably going to be part of the fun
Jacob Lifshay (Jul 20 2025 at 19:53):well, if/when you want to make another small cpu for fun, i'd recommend using the RISC-V rv32i instruction set since it's pretty simple and open (unlike arm) and there are existing good compilers (gcc and anything llvm-based like clang or rustc).
Jacob Lifshay (Jul 20 2025 at 20:07):e.g. here's a simple implementation of a rv32i cpu that I wrote in several hours as a demo of how cpus work for a friend, I won't claim it doesn't have bugs since i did very little testing, but it implements all the instructions you'd need for running single-threaded code -- it doesn't implement the fence (for multi-threaded code or DMA) and ecall/ebreak instructions (for operating system calls and debugging breakpoints). btw i mean simple as in easy to write, not as in the simplest circuit
Trevor Klingler (Jul 20 2025 at 20:12):Making a RISC-V CPU is certainly a project I'm interested in! I have an FPGA board that I think would be tons of fun to make an emulated CPU in. It's been a while since I've played with verilog and that would be a great excuse. I certainly think that you're correct that if making a working CPU was my goal, that'd be the best way to do it, but mostly I think this would be a cool project.
Plus, this could open the door down the line if, for example, I find myself wanting to target a microcontroller with a toolchain that's incompatible with the rust compiler and I want to add support. Obviously, in that case, it would probably make more sense to add that target to LLVM, but that sounds less fun to me!
Thanks for that example CPU by the way, I may use that for reference down the road ;D
Jacob Lifshay (Jul 20 2025 at 20:15):i'm not that familiar with how to create a new cranelift backend, so I'll let others answer that part
Trevor Klingler (Jul 20 2025 at 20:26):ok, thanks for your input!
Chris Fallin (Jul 21 2025 at 15:21):I'd be happy to work through this and write up a guide (maybe a blog post or something) for future contributors so that others have a starting point for creating a new ISA, but before I fully commit to the project, I wanted to get people's impressions here of the feasibility of doing this, and their thoughts on the best way to get started.
Yes, documentation for this thing in particular is something we've wanted for a while and have never had time to write up. It would be very much appreciated if you contributed something like this!
In the past when folks ask about the effort to create a new backend for Cranelift, I've estimated the effort at around 3 months' fulltime work and 20k lines of code. The latter at least is (still) about the scale of our existing backends. That's of course for the full gamut of features that we support; copying+pasting from riscv64, ripping out vectors and stripping the ABI down to register args only and removing a bunch of optimized lowering rules, one could probably get substantially smaller.
Trevor Klingler (Jul 22 2025 at 02:38):ok, I'll start looking at simply copying the riscv and ripping out anything that's not strictly necessary. In fact, just doing that and having a working minimal example of an ISA probably accomplishes exactly my objective, as well as being perhaps the most useful way to start documentation on creating a backend.
Are there any other places in the code that I should be aware of before starting to undertake that work? Also, I see those *.isle files, but my cursory searches haven't turned anything up. Is that a custom format? Does any documentation on those exist anywhere?
I can't make any promises because of my current time commitments, (not to mention I'm serial project starter, but not finisher), but I'll start putting some time towards it when I have time here or there.
Chris Fallin (Jul 22 2025 at 02:53):ISLE files are our own DSL for defining instruction lowering rules -- as you write a new backend you will definitely become familiar with it! A few starting points:
Chris Fallin (Jul 22 2025 at 02:54):(for points of comparison, various compiler projects have DSLs to define sets of rules/rewrites -- see e.g. LLVM's TableGen or Go's S-expression-based rule system. ISLE is in the same general category as those, though differs in a bunch of ways too)
Trevor Klingler (Jul 22 2025 at 02:55):sounds like a great place to start, thanks!
Last updated: Dec 06 2025 at 07:03 UTC