Stream: cranelift

Topic: Aarch64 missing MovFromFpu instruction?


view this post on Zulip minirop (Dec 10 2024 at 20:43):

hello.

Working on winch, I have to bitcast float to/from int. I found Inst::MovToFpu that generate fmov sX, wX or fmov dX, xX but there are nothing to do the opposite (i.e. fmov wX, sX or fmov xX, dX).
Is this an oversight or I'm missing something?

regards

A lightweight WebAssembly runtime that is fast, secure, and standards-compliant - bytecodealliance/wasmtime

view this post on Zulip Saúl Cabrera (Dec 10 2024 at 21:44):

We have a helper in the aarch64 assembler: mov_from_vec, which I think is what you'd need to use here. By the way, we also have the #winch stream, for Winch related questions. Feel free to post any other Winch-related discussion there!

view this post on Zulip minirop (Dec 11 2024 at 12:50):

I posted here because it's about cranelift-codegen, but looking at mov_from_vec I understand that fmov w1, s2 is equivalent to mov w1, v2.s[0]?

view this post on Zulip Saúl Cabrera (Dec 11 2024 at 13:14):

Yeah, that's correct. Moving from lane 0 of the fpu source register.


Last updated: Dec 23 2024 at 13:07 UTC