marin (Dec 12 2024 at 00:03): marin (Dec 12 2024 at 00:03):I'm working on implementing 32bit divsion in cranelift and winch, and I notice that a lot of intructions have the size bit hard-coded to 1, but not always. For example, ALU op is inconsistent, with most of them being encoded as 32 bits, and others as 64bits, while cbz, is hardcoded to 64 bits. Is there some reason for that, of is this simply accidental?
for ref: https://github.com/bytecodealliance/wasmtime/blob/main/cranelift/codegen/src/isa/aarch64/inst/emit.rs#L736-L755, notice the first bit
marin (Dec 12 2024 at 00:05):As a followup, should we rather introduce new instructions when a size variant is required, or patch existing ones?
Chris Fallin (Dec 13 2024 at 22:24):This is almost certainly a case of "that variant is all we've needed so far"; we can definitely add the 32-bit variants
Chris Fallin (Dec 13 2024 at 22:24):Probably an enum field in the existing instruction is best (OperandSize or equivalent) rather than a whole new variant of the Inst
marin (Dec 13 2024 at 22:55):Ok, I think this is the approach I have ended up taking here, in the end: https://github.com/bytecodealliance/wasmtime/pull/9798
Chris Fallin (Dec 13 2024 at 22:57):ah, cool, sorry I hadn't connected the dots with the PR :-) I'll go review that
marin (Dec 13 2024 at 22:57):NP, i'm in no rush anyway :)
Last updated: Dec 23 2024 at 12:05 UTC