✔ regalloc2: Different Source And Destination Registers · cranelift

Stream: cranelift

Topic: ✔ regalloc2: Different Source And Destination Registers

Afonso Bordado (May 29 2023 at 15:42):

:wave: Hey,

I'm working on implementing swizzle on RISC-V. This pretty much has a 1-1 translation with the vrgather.vv instruction in the V Spec. However that instruction has an interesting encoding constrain in that the source registers must never be the same as the destination registers.

I couldn't find any way of modeling this constraint in regalloc2. Did I miss something? And failing that, do we have any good ways of doing it other than using a fixed register constraint?

riscv-v-spec/v-spec.adoc at master · riscv/riscv-v-spec

Working draft of the proposed RISC-V V vector extension - riscv-v-spec/v-spec.adoc at master · riscv/riscv-v-spec

Afonso Bordado (May 29 2023 at 15:51):

Now that I'm looking at this again, it looks like we can use reg_def_at_start and reg_use_at_end to specify this constraint. Not sure how I missed those, Sorry for the noise!

Notification Bot (May 29 2023 at 15:51):

Afonso Bordado has marked this topic as resolved.

Last updated: Oct 23 2024 at 20:03 UTC