CompilerSmith (Apr 04 2024 at 17:38): CompilerSmith (Apr 04 2024 at 17:38):I have a quick question about regalloc2. It seems that the library does not care or require you to specify the bitwidth of the virtual register. VReg does not have any way to express the bitwidth needed.
If i have a 32bit value in a virtual register in IR how do i tell the register allocator about the size?
https://docs.rs/regalloc2/0.9.3/regalloc2/struct.VReg.html
Refering to documentation here^
Notification Bot (Apr 04 2024 at 17:41):This topic was moved here from #general > regalloc2 question by fitzgen (he/him).
Chris Fallin (Apr 04 2024 at 17:43):@CompilerSmith you're correct, the register allocator doesn't care about the width of values -- that's because it operates in units of registers, not values. In other words, the mapping from "value" to "register" is at a higher semantic level, and by the time code reaches the register allocator, it is purely operating on registers only
Chris Fallin (Apr 04 2024 at 17:44):Concretely, what changes in the output would you want, based on the size? The one thing I can think of is using a smaller spillslot than the whole register; we explicitly designed not to do that, both because spillslots can be shared by vregs (some of which may have narrow types and some of which may not), and because we historically had a bad CVE related to that in 2021, so I'm personally suspicious of attempts to make use of "narrowness" information; it becomes very counterintuitive when writing instruction lowerings that vregs may not be fully carried through
Notification Bot (Apr 04 2024 at 17:57):CompilerSmith has marked this topic as resolved.
CompilerSmith (Apr 04 2024 at 18:00):Chris Fallin said:
Concretely, what changes in the output would you want, based on the size? The one thing I can think of is using a smaller spillslot than the whole register; we explicitly designed not to do that, both because spillslots can be shared by vregs (some of which may have narrow types and some of which may not), and because we historically had a bad CVE related to that in 2021, so I'm personally suspicious of attempts to make use of "narrowness" information; it becomes very counterintuitive when writing instruction lowerings that vregs may not be fully carried through
Thank you for the answer, and sorry for the double post I didnt see it got moved.
This makes sense. I suppose i can allocate the entire register and then just use the size i need of it. I'm writing my own little IR that works closely with x86 semantics. I am re-register allocating already compiled functions. The algorithm/framework should still work for me i will just make a MachineEnv with the full width registers and then when the algorithm allocates for me i will just use the width of the register i need.
Last updated: Dec 23 2024 at 13:07 UTC