Stream: cranelift

Topic: ✔ Implementing a backend for simple architecture (VM)

Jakub Dóka (Sep 16 2024 at 16:19):

Hello,

I am implementing a compiler for a VM that runs on a niche operating system.

The instructions are similar to ARM architecture and I already wrote a single-pass compiler. Still, the resulting code is comparatively slow (since every instruction matters on the VM). I started working on the Sea-Of-Nodes backend and got stuck on register allocation. At this point, I have 3 options:

1. Try harder and come up with my own register allocator
2. Use regalloc2
3. Implement target ISA and use Cranelift

I am tempted by 3. and I also saw this issue that could be resolved. This would also make compiling to native easier for me.

I guess the question is:

1. How hard can 3. be and is it even a good idea compared to my other options? (I heard LLVM requires 20k sloc minimum to do this. I am hoping this is not the case with Cranelift.)
2. Where can I find some resources on how to do this? (The issue I mentioned implies the code is the only source of truth, but maybe that's outdated?)

bjorn3 (Sep 16 2024 at 16:27):

heard LLVM requires 20k sloc minimum to do this. I am hoping this is not the case with Cranelift.

The x86_64 backend is 18k, the arm64 one is 18k, the riscv64 one is 11k and the s390x one is 22k. All of these are complete enough for both wasmtime and rustc_codegen_cranelift to function. This includes floats, 128bit ints, atomics, thread local storage and simd. If you don't need any of these features, you can probably write a backend in a fair bit less code. (10k maybe? just a wild guess)

bjorn3 (Sep 16 2024 at 16:30):

Where can I find some resources on how to do this? (The issue I mentioned implies the code is the only source of truth, but maybe that's outdated?)

cranelift/isle/docs/language-reference.md has a description of the ISLE DSL we use for defining lowerings. (Some details may no longer be correct, but the high level overview is still correct.)

bjorn3 (Sep 16 2024 at 16:31):

As for the rest of the backend, reading up on what other backends do and asking questions if something is unclear is probably the best option you have right now. There are not a whole lot of docs.

Jakub Dóka (Sep 17 2024 at 08:55):

Okay, thanks for the leads @bjorn3, I have decided to try and copy the RISCV backend from the cranelift_codegen to a crate in my project and to make it compile. I managed to generate ISLE, but some modules that RISCV uses like machinst, abi, and result are private, so I probably won't manage that. How useful would these modules be to me if they were to be made public?

bjorn3 (Sep 17 2024 at 11:54):

All types in the result module are re-exported at the root of cranelift_codegen. I'm not sure which abi module you mean. There is one in machinst and one in the arch::riscv64 module. As for machinst it should in principle be useful, however it doesn't have the same level of stability as the rest of cranelift.

Jakub Dóka (Sep 17 2024 at 12:23):

I can't actually implement TargetIsa outside of the cranelift_codegen because it uses CompiledCodeBase<Stencil> in the fn compile_function. This is a hard block, I might fork the Wasmtime for the time being and make the machinst public...

Jakub Dóka (Sep 20 2024 at 15:41):

After some trying, I determined this is too big of a chore to implement, bigger than just using the crane lift backend in addition to my own optimizing compiler if I end up compiling to native, I also already managed to use regalloc2 so the problem is resolved for the time being, but thanx for help anyway!

Notification Bot (Sep 20 2024 at 15:41):

Jakub Dóka has marked this topic as resolved.

Last updated: Oct 23 2024 at 20:03 UTC