atomic store a value can fail.
https://msyksphinz-self.github.io/riscv-isadoc/html/rv64a.html#sc-d
should I use a loop to implement atomic store.
loop {
sc.d rd,rs1,rs2
if rd == 0 break;
}
hi @yang yu -- actually the semantics of Cranelift's atomic store are infallible, i.e., there is no "failure". I think you may be confusing it for a "store conditional" (sc
in RISC-V or other classic RISCs like MIPS, ARM32) instruction, which fails if some other CPU touched the value since the paired "load-linked"
an atomic store should have SeqCst ordering, which means that it occurs in some order relative to other atomic loads/stores on the same address and all CPUs agree on that order, and it also imposes ordering edges on the surrounding program (ordinary loads/stores prior to an atomic store always come before, and are observed by, ordinary loads/stores after an atomic load that observes the atomic store)
You'll need to reason about the memory model -- I don't know in detail what RISC-V provides -- but probably what you'll need is an ordinary store instruction, preceded by and/or followed by a memory fence or barrier instruction of some kind
one easy way to see what should be generated is to use an atomic with SeqCst ordering in C++ or Rust, and compile it to assembly; then do whatever clang or rustc does
here are atomic loads and stores with SeqCst in Rust, compiled to RISC-V: https://godbolt.org/z/G5h4c3cxc
@Chris Fallin thanks , But I am not very understand this. May be I will find some course to learn about this.
@yang yu for now I think just emitting the same output as what you see from rustc
(in the Godbolt compiler explorer link above) should be fine
ok
yang yu has marked this topic as resolved.
Last updated: Dec 23 2024 at 12:05 UTC