gimli/
arch.rs

1use crate::common::Register;
2
3macro_rules! registers {
4    ($struct_name:ident, { $($name:ident = ($val:expr, $disp:expr)),+ $(,)? }
5        $(, aliases { $($alias_name:ident = ($alias_val:expr, $alias_disp:expr)),+ $(,)? })?) => {
6        #[allow(missing_docs)]
7        impl $struct_name {
8            $(
9                pub const $name: Register = Register($val);
10            )+
11            $(
12                $(pub const $alias_name: Register = Register($alias_val);)+
13            )*
14        }
15
16        impl $struct_name {
17            /// The name of a register, or `None` if the register number is unknown.
18            ///
19            /// Only returns the primary name for registers that alias with others.
20            pub fn register_name(register: Register) -> Option<&'static str> {
21                match register {
22                    $(
23                        Self::$name => Some($disp),
24                    )+
25                    _ => return None,
26                }
27            }
28
29	    /// Converts a register name into a register number.
30	    pub fn name_to_register(value: &str) -> Option<Register> {
31		match value {
32                    $(
33                        $disp => Some(Self::$name),
34                    )+
35                    $(
36                        $($alias_disp => Some(Self::$alias_name),)+
37                    )*
38                    _ => return None,
39		}
40	    }
41        }
42    };
43}
44
45/// ARM architecture specific definitions.
46///
47/// See [DWARF for the ARM Architecture](
48/// https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst).
49#[derive(Debug, Clone, Copy)]
50pub struct Arm;
51
52registers!(Arm, {
53    R0 = (0, "R0"),
54    R1 = (1, "R1"),
55    R2 = (2, "R2"),
56    R3 = (3, "R3"),
57    R4 = (4, "R4"),
58    R5 = (5, "R5"),
59    R6 = (6, "R6"),
60    R7 = (7, "R7"),
61    R8 = (8, "R8"),
62    R9 = (9, "R9"),
63    R10 = (10, "R10"),
64    R11 = (11, "R11"),
65    R12 = (12, "R12"),
66    R13 = (13, "R13"),
67    R14 = (14, "R14"),
68    R15 = (15, "R15"),
69
70    WCGR0 = (104, "wCGR0"),
71    WCGR1 = (105, "wCGR1"),
72    WCGR2 = (106, "wCGR2"),
73    WCGR3 = (107, "wCGR3"),
74    WCGR4 = (108, "wCGR4"),
75    WCGR5 = (109, "wCGR5"),
76    WCGR6 = (110, "wCGR6"),
77    WCGR7 = (111, "wCGR7"),
78
79    WR0 = (112, "wR0"),
80    WR1 = (113, "wR1"),
81    WR2 = (114, "wR2"),
82    WR3 = (115, "wR3"),
83    WR4 = (116, "wR4"),
84    WR5 = (117, "wR5"),
85    WR6 = (118, "wR6"),
86    WR7 = (119, "wR7"),
87    WR8 = (120, "wR8"),
88    WR9 = (121, "wR9"),
89    WR10 = (122, "wR10"),
90    WR11 = (123, "wR11"),
91    WR12 = (124, "wR12"),
92    WR13 = (125, "wR13"),
93    WR14 = (126, "wR14"),
94    WR15 = (127, "wR15"),
95
96    SPSR = (128, "SPSR"),
97    SPSR_FIQ = (129, "SPSR_FIQ"),
98    SPSR_IRQ = (130, "SPSR_IRQ"),
99    SPSR_ABT = (131, "SPSR_ABT"),
100    SPSR_UND = (132, "SPSR_UND"),
101    SPSR_SVC = (133, "SPSR_SVC"),
102
103    RA_AUTH_CODE = (143, "RA_AUTH_CODE"),
104
105    R8_USR = (144, "R8_USR"),
106    R9_USR = (145, "R9_USR"),
107    R10_USR = (146, "R10_USR"),
108    R11_USR = (147, "R11_USR"),
109    R12_USR = (148, "R12_USR"),
110    R13_USR = (149, "R13_USR"),
111    R14_USR = (150, "R14_USR"),
112
113    R8_FIQ = (151, "R8_FIQ"),
114    R9_FIQ = (152, "R9_FIQ"),
115    R10_FIQ = (153, "R10_FIQ"),
116    R11_FIQ = (154, "R11_FIQ"),
117    R12_FIQ = (155, "R12_FIQ"),
118    R13_FIQ = (156, "R13_FIQ"),
119    R14_FIQ = (157, "R14_FIQ"),
120
121    R13_IRQ = (158, "R13_IRQ"),
122    R14_IRQ = (159, "R14_IRQ"),
123
124    R13_ABT = (160, "R13_ABT"),
125    R14_ABT = (161, "R14_ABT"),
126
127    R13_UND = (162, "R13_UND"),
128    R14_UND = (163, "R14_UND"),
129
130    R13_SVC = (164, "R13_SVC"),
131    R14_SVC = (165, "R14_SVC"),
132
133    WC0 = (192, "wC0"),
134    WC1 = (193, "wC1"),
135    WC2 = (194, "wC2"),
136    WC3 = (195, "wC3"),
137    WC4 = (196, "wC4"),
138    WC5 = (197, "wC5"),
139    WC6 = (198, "wC6"),
140    WC7 = (199, "wC7"),
141
142    D0 = (256, "D0"),
143    D1 = (257, "D1"),
144    D2 = (258, "D2"),
145    D3 = (259, "D3"),
146    D4 = (260, "D4"),
147    D5 = (261, "D5"),
148    D6 = (262, "D6"),
149    D7 = (263, "D7"),
150    D8 = (264, "D8"),
151    D9 = (265, "D9"),
152    D10 = (266, "D10"),
153    D11 = (267, "D11"),
154    D12 = (268, "D12"),
155    D13 = (269, "D13"),
156    D14 = (270, "D14"),
157    D15 = (271, "D15"),
158    D16 = (272, "D16"),
159    D17 = (273, "D17"),
160    D18 = (274, "D18"),
161    D19 = (275, "D19"),
162    D20 = (276, "D20"),
163    D21 = (277, "D21"),
164    D22 = (278, "D22"),
165    D23 = (279, "D23"),
166    D24 = (280, "D24"),
167    D25 = (281, "D25"),
168    D26 = (282, "D26"),
169    D27 = (283, "D27"),
170    D28 = (284, "D28"),
171    D29 = (285, "D29"),
172    D30 = (286, "D30"),
173    D31 = (287, "D31"),
174
175    TPIDRURO = (320, "TPIDRURO"),
176    TPIDRURW = (321, "TPIDRURW"),
177    TPIDPR = (322, "TPIDPR"),
178    HTPIDPR = (323, "HTPIDPR"),
179},
180aliases {
181    SP = (13, "SP"),
182    LR = (14, "LR"),
183    PC = (15, "PC"),
184
185    ACC0 = (104, "ACC0"),
186    ACC1 = (105, "ACC1"),
187    ACC2 = (106, "ACC2"),
188    ACC3 = (107, "ACC3"),
189    ACC4 = (108, "ACC4"),
190    ACC5 = (109, "ACC5"),
191    ACC6 = (110, "ACC6"),
192    ACC7 = (111, "ACC7"),
193
194    S0 = (256, "S0"),
195    S1 = (256, "S1"),
196    S2 = (257, "S2"),
197    S3 = (257, "S3"),
198    S4 = (258, "S4"),
199    S5 = (258, "S5"),
200    S6 = (259, "S6"),
201    S7 = (259, "S7"),
202    S8 = (260, "S8"),
203    S9 = (260, "S9"),
204    S10 = (261, "S10"),
205    S11 = (261, "S11"),
206    S12 = (262, "S12"),
207    S13 = (262, "S13"),
208    S14 = (263, "S14"),
209    S15 = (263, "S15"),
210    S16 = (264, "S16"),
211    S17 = (264, "S17"),
212    S18 = (265, "S18"),
213    S19 = (265, "S19"),
214    S20 = (266, "S20"),
215    S21 = (266, "S21"),
216    S22 = (267, "S22"),
217    S23 = (267, "S23"),
218    S24 = (268, "S24"),
219    S25 = (268, "S25"),
220    S26 = (269, "S26"),
221    S27 = (269, "S27"),
222    S28 = (270, "S28"),
223    S29 = (270, "S29"),
224    S30 = (271, "S30"),
225    S31 = (271, "S31"),
226});
227
228/// ARM 64-bit (AArch64) architecture specific definitions.
229///
230/// See [DWARF for the ARM 64-bit Architecture](
231/// https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst).
232#[derive(Debug, Clone, Copy)]
233pub struct AArch64;
234
235registers!(AArch64, {
236    X0 = (0, "X0"),
237    X1 = (1, "X1"),
238    X2 = (2, "X2"),
239    X3 = (3, "X3"),
240    X4 = (4, "X4"),
241    X5 = (5, "X5"),
242    X6 = (6, "X6"),
243    X7 = (7, "X7"),
244    X8 = (8, "X8"),
245    X9 = (9, "X9"),
246    X10 = (10, "X10"),
247    X11 = (11, "X11"),
248    X12 = (12, "X12"),
249    X13 = (13, "X13"),
250    X14 = (14, "X14"),
251    X15 = (15, "X15"),
252    X16 = (16, "X16"),
253    X17 = (17, "X17"),
254    X18 = (18, "X18"),
255    X19 = (19, "X19"),
256    X20 = (20, "X20"),
257    X21 = (21, "X21"),
258    X22 = (22, "X22"),
259    X23 = (23, "X23"),
260    X24 = (24, "X24"),
261    X25 = (25, "X25"),
262    X26 = (26, "X26"),
263    X27 = (27, "X27"),
264    X28 = (28, "X28"),
265    X29 = (29, "X29"),
266    X30 = (30, "X30"),
267    SP = (31, "SP"),
268    PC = (32, "PC"),
269    ELR_MODE = (33, "ELR_mode"),
270    RA_SIGN_STATE = (34, "RA_SIGN_STATE"),
271    TPIDRRO_EL0 = (35, "TPIDRRO_EL0"),
272    TPIDR_EL0 = (36, "TPIDR_EL0"),
273    TPIDR_EL1 = (37, "TPIDR_EL1"),
274    TPIDR_EL2 = (38, "TPIDR_EL2"),
275    TPIDR_EL3 = (39, "TPIDR_EL3"),
276
277    VG = (46, "VG"),
278    FFR = (47, "FFR"),
279
280    P0 = (48, "P0"),
281    P1 = (49, "P1"),
282    P2 = (50, "P2"),
283    P3 = (51, "P3"),
284    P4 = (52, "P4"),
285    P5 = (53, "P5"),
286    P6 = (54, "P6"),
287    P7 = (55, "P7"),
288    P8 = (56, "P8"),
289    P9 = (57, "P9"),
290    P10 = (58, "P10"),
291    P11 = (59, "P11"),
292    P12 = (60, "P12"),
293    P13 = (61, "P13"),
294    P14 = (62, "P14"),
295    P15 = (63, "P15"),
296
297    V0 = (64, "V0"),
298    V1 = (65, "V1"),
299    V2 = (66, "V2"),
300    V3 = (67, "V3"),
301    V4 = (68, "V4"),
302    V5 = (69, "V5"),
303    V6 = (70, "V6"),
304    V7 = (71, "V7"),
305    V8 = (72, "V8"),
306    V9 = (73, "V9"),
307    V10 = (74, "V10"),
308    V11 = (75, "V11"),
309    V12 = (76, "V12"),
310    V13 = (77, "V13"),
311    V14 = (78, "V14"),
312    V15 = (79, "V15"),
313    V16 = (80, "V16"),
314    V17 = (81, "V17"),
315    V18 = (82, "V18"),
316    V19 = (83, "V19"),
317    V20 = (84, "V20"),
318    V21 = (85, "V21"),
319    V22 = (86, "V22"),
320    V23 = (87, "V23"),
321    V24 = (88, "V24"),
322    V25 = (89, "V25"),
323    V26 = (90, "V26"),
324    V27 = (91, "V27"),
325    V28 = (92, "V28"),
326    V29 = (93, "V29"),
327    V30 = (94, "V30"),
328    V31 = (95, "V31"),
329
330    Z0 = (96, "Z0"),
331    Z1 = (97, "Z1"),
332    Z2 = (98, "Z2"),
333    Z3 = (99, "Z3"),
334    Z4 = (100, "Z4"),
335    Z5 = (101, "Z5"),
336    Z6 = (102, "Z6"),
337    Z7 = (103, "Z7"),
338    Z8 = (104, "Z8"),
339    Z9 = (105, "Z9"),
340    Z10 = (106, "Z10"),
341    Z11 = (107, "Z11"),
342    Z12 = (108, "Z12"),
343    Z13 = (109, "Z13"),
344    Z14 = (110, "Z14"),
345    Z15 = (111, "Z15"),
346    Z16 = (112, "Z16"),
347    Z17 = (113, "Z17"),
348    Z18 = (114, "Z18"),
349    Z19 = (115, "Z19"),
350    Z20 = (116, "Z20"),
351    Z21 = (117, "Z21"),
352    Z22 = (118, "Z22"),
353    Z23 = (119, "Z23"),
354    Z24 = (120, "Z24"),
355    Z25 = (121, "Z25"),
356    Z26 = (122, "Z26"),
357    Z27 = (123, "Z27"),
358    Z28 = (124, "Z28"),
359    Z29 = (125, "Z29"),
360    Z30 = (126, "Z30"),
361    Z31 = (127, "Z31"),
362});
363
364/// LoongArch architecture specific definitions.
365///
366/// See [LoongArch ELF psABI specification](https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html).
367#[derive(Debug, Clone, Copy)]
368pub struct LoongArch;
369
370registers!(LoongArch, {
371    R0 = (0, "$r0"),
372    R1 = (1, "$r1"),
373    R2 = (2, "$r2"),
374    R3 = (3, "$r3"),
375    R4 = (4, "$r4"),
376    R5 = (5, "$r5"),
377    R6 = (6, "$r6"),
378    R7 = (7, "$r7"),
379    R8 = (8, "$r8"),
380    R9 = (9, "$r9"),
381    R10 = (10, "$r10"),
382    R11 = (11, "$r11"),
383    R12 = (12, "$r12"),
384    R13 = (13, "$r13"),
385    R14 = (14, "$r14"),
386    R15 = (15, "$r15"),
387    R16 = (16, "$r16"),
388    R17 = (17, "$r17"),
389    R18 = (18, "$r18"),
390    R19 = (19, "$r19"),
391    R20 = (20, "$r20"),
392    R21 = (21, "$r21"),
393    R22 = (22, "$r22"),
394    R23 = (23, "$r23"),
395    R24 = (24, "$r24"),
396    R25 = (25, "$r25"),
397    R26 = (26, "$r26"),
398    R27 = (27, "$r27"),
399    R28 = (28, "$r28"),
400    R29 = (29, "$r29"),
401    R30 = (30, "$r30"),
402    R31 = (31, "$r31"),
403
404    F0 = (32, "$f0"),
405    F1 = (33, "$f1"),
406    F2 = (34, "$f2"),
407    F3 = (35, "$f3"),
408    F4 = (36, "$f4"),
409    F5 = (37, "$f5"),
410    F6 = (38, "$f6"),
411    F7 = (39, "$f7"),
412    F8 = (40, "$f8"),
413    F9 = (41, "$f9"),
414    F10 = (42, "$f10"),
415    F11 = (43, "$f11"),
416    F12 = (44, "$f12"),
417    F13 = (45, "$f13"),
418    F14 = (46, "$f14"),
419    F15 = (47, "$f15"),
420    F16 = (48, "$f16"),
421    F17 = (49, "$f17"),
422    F18 = (50, "$f18"),
423    F19 = (51, "$f19"),
424    F20 = (52, "$f20"),
425    F21 = (53, "$f21"),
426    F22 = (54, "$f22"),
427    F23 = (55, "$f23"),
428    F24 = (56, "$f24"),
429    F25 = (57, "$f25"),
430    F26 = (58, "$f26"),
431    F27 = (59, "$f27"),
432    F28 = (60, "$f28"),
433    F29 = (61, "$f29"),
434    F30 = (62, "$f30"),
435    F31 = (63, "$f31"),
436    FCC0 = (64, "$fcc0"),
437    FCC1 = (65, "$fcc1"),
438    FCC2 = (66, "$fcc2"),
439    FCC3 = (67, "$fcc3"),
440    FCC4 = (68, "$fcc4"),
441    FCC5 = (69, "$fcc5"),
442    FCC6 = (70, "$fcc6"),
443    FCC7 = (71, "$fcc7"),
444},
445aliases {
446    ZERO = (0, "$zero"),
447    RA = (1, "$ra"),
448    TP = (2, "$tp"),
449    SP = (3, "$sp"),
450    A0 = (4, "$a0"),
451    A1 = (5, "$a1"),
452    A2 = (6, "$a2"),
453    A3 = (7, "$a3"),
454    A4 = (8, "$a4"),
455    A5 = (9, "$a5"),
456    A6 = (10, "$a6"),
457    A7 = (11, "$a7"),
458    T0 = (12, "$t0"),
459    T1 = (13, "$t1"),
460    T2 = (14, "$t2"),
461    T3 = (15, "$t3"),
462    T4 = (16, "$t4"),
463    T5 = (17, "$t5"),
464    T6 = (18, "$t6"),
465    T7 = (19, "$t7"),
466    T8 = (20, "$t8"),
467    FP = (22, "$fp"),
468    S0 = (23, "$s0"),
469    S1 = (24, "$s1"),
470    S2 = (25, "$s2"),
471    S3 = (26, "$s3"),
472    S4 = (27, "$s4"),
473    S5 = (28, "$s5"),
474    S6 = (29, "$s6"),
475    S7 = (30, "$s7"),
476    S8 = (31, "$s8"),
477
478    FA0 = (32, "$fa0"),
479    FA1 = (33, "$fa1"),
480    FA2 = (34, "$fa2"),
481    FA3 = (35, "$fa3"),
482    FA4 = (36, "$fa4"),
483    FA5 = (37, "$fa5"),
484    FA6 = (38, "$fa6"),
485    FA7 = (39, "$fa7"),
486    FT0 = (40, "$ft0"),
487    FT1 = (41, "$ft1"),
488    FT2 = (42, "$ft2"),
489    FT3 = (43, "$ft3"),
490    FT4 = (44, "$ft4"),
491    FT5 = (45, "$ft5"),
492    FT6 = (46, "$ft6"),
493    FT7 = (47, "$ft7"),
494    FT8 = (48, "$ft8"),
495    FT9 = (49, "$ft9"),
496    FT10 = (50, "$ft10"),
497    FT11 = (51, "$ft11"),
498    FT12 = (52, "$ft12"),
499    FT13 = (53, "$ft13"),
500    FT14 = (54, "$ft14"),
501    FT15 = (55, "$ft15"),
502    FS0 = (56, "$fs0"),
503    FS1 = (57, "$fs1"),
504    FS2 = (58, "$fs2"),
505    FS3 = (59, "$fs3"),
506    FS4 = (60, "$fs4"),
507    FS5 = (61, "$fs5"),
508    FS6 = (62, "$fs6"),
509    FS7 = (63, "$fs7"),
510});
511
512/// MIPS architecture specific definitions.
513///
514/// See [MIPS Details](https://en.wikibooks.org/wiki/MIPS_Assembly/MIPS_Details).
515#[derive(Debug, Clone, Copy)]
516pub struct MIPS;
517
518registers!(MIPS, {
519    R0 = (0, "$0"),
520    R1 = (1, "$1"),
521    R2 = (2, "$2"),
522    R3 = (3, "$3"),
523    R4 = (4, "$4"),
524    R5 = (5, "$5"),
525    R6 = (6, "$6"),
526    R7 = (7, "$7"),
527    R8 = (8, "$8"),
528    R9 = (9, "$9"),
529    R10 = (10, "$10"),
530    R11 = (11, "$11"),
531    R12 = (12, "$12"),
532    R13 = (13, "$13"),
533    R14 = (14, "$14"),
534    R15 = (15, "$15"),
535    R16 = (16, "$16"),
536    R17 = (17, "$17"),
537    R18 = (18, "$18"),
538    R19 = (19, "$19"),
539    R20 = (20, "$20"),
540    R21 = (21, "$21"),
541    R22 = (22, "$22"),
542    R23 = (23, "$23"),
543    R24 = (24, "$24"),
544    R25 = (25, "$25"),
545    R26 = (26, "$26"),
546    R27 = (27, "$27"),
547    R28 = (28, "$28"),
548    R29 = (29, "$29"),
549    R30 = (30, "$30"),
550    R31 = (31, "$31"),
551
552    F0 = (32, "$f0"),
553    F1 = (33, "$f1"),
554    F2 = (34, "$f2"),
555    F3 = (35, "$f3"),
556    F4 = (36, "$f4"),
557    F5 = (37, "$f5"),
558    F6 = (38, "$f6"),
559    F7 = (39, "$f7"),
560    F8 = (40, "$f8"),
561    F9 = (41, "$f9"),
562    F10 = (42, "$f10"),
563    F11 = (43, "$f11"),
564    F12 = (44, "$f12"),
565    F13 = (45, "$f13"),
566    F14 = (46, "$f14"),
567    F15 = (47, "$f15"),
568    F16 = (48, "$f16"),
569    F17 = (49, "$f17"),
570    F18 = (50, "$f18"),
571    F19 = (51, "$f19"),
572    F20 = (52, "$f20"),
573    F21 = (53, "$f21"),
574    F22 = (54, "$f22"),
575    F23 = (55, "$f23"),
576    F24 = (56, "$f24"),
577    F25 = (57, "$f25"),
578    F26 = (58, "$f26"),
579    F27 = (59, "$f27"),
580    F28 = (60, "$f28"),
581    F29 = (61, "$f29"),
582    F30 = (62, "$f30"),
583    F31 = (63, "$f31"),
584
585    HI = (64, "$hi"),
586    LO = (65, "$lo"),
587},
588aliases {
589    ZERO = (0, "$zero"),
590    AT = (1, "$at"),
591    V0 = (2, "$v0"),
592    V1 = (3, "$v1"),
593    A0 = (4, "$a0"),
594    A1 = (5, "$a1"),
595    A2 = (6, "$a2"),
596    A3 = (7, "$a3"),
597    T0 = (8, "$t0"),
598    T1 = (9, "$t1"),
599    T2 = (10, "$t2"),
600    T3 = (11, "$t3"),
601    T4 = (12, "$t4"),
602    T5 = (13, "$t5"),
603    T6 = (14, "$t6"),
604    T7 = (15, "$t7"),
605    S0 = (16, "$s0"),
606    S1 = (17, "$s1"),
607    S2 = (18, "$s2"),
608    S3 = (19, "$s3"),
609    S4 = (20, "$s4"),
610    S5 = (21, "$s5"),
611    S6 = (22, "$s6"),
612    S7 = (23, "$s7"),
613    T8 = (24, "$t8"),
614    T9 = (25, "$t9"),
615    K0 = (26, "$k0"),
616    K1 = (27, "$k1"),
617    GP = (28, "$gp"),
618    SP = (29, "$sp"),
619    FP = (30, "$fp"),
620    RA = (31, "$ra"),
621
622    S8 = (30, "$s8")
623});
624
625/// RISC-V architecture specific definitions.
626///
627/// See [RISC-V ELF psABI specification](https://github.com/riscv/riscv-elf-psabi-doc).
628#[derive(Debug, Clone, Copy)]
629pub struct RiscV;
630
631registers!(RiscV, {
632    X0 = (0, "x0"),
633    X1 = (1, "x1"),
634    X2 = (2, "x2"),
635    X3 = (3, "x3"),
636    X4 = (4, "x4"),
637    X5 = (5, "x5"),
638    X6 = (6, "x6"),
639    X7 = (7, "x7"),
640    X8 = (8, "x8"),
641    X9 = (9, "x9"),
642    X10 = (10, "x10"),
643    X11 = (11, "x11"),
644    X12 = (12, "x12"),
645    X13 = (13, "x13"),
646    X14 = (14, "x14"),
647    X15 = (15, "x15"),
648    X16 = (16, "x16"),
649    X17 = (17, "x17"),
650    X18 = (18, "x18"),
651    X19 = (19, "x19"),
652    X20 = (20, "x20"),
653    X21 = (21, "x21"),
654    X22 = (22, "x22"),
655    X23 = (23, "x23"),
656    X24 = (24, "x24"),
657    X25 = (25, "x25"),
658    X26 = (26, "x26"),
659    X27 = (27, "x27"),
660    X28 = (28, "x28"),
661    X29 = (29, "x29"),
662    X30 = (30, "x30"),
663    X31 = (31, "x31"),
664
665    F0 = (32, "f0"),
666    F1 = (33, "f1"),
667    F2 = (34, "f2"),
668    F3 = (35, "f3"),
669    F4 = (36, "f4"),
670    F5 = (37, "f5"),
671    F6 = (38, "f6"),
672    F7 = (39, "f7"),
673    F8 = (40, "f8"),
674    F9 = (41, "f9"),
675    F10 = (42, "f10"),
676    F11 = (43, "f11"),
677    F12 = (44, "f12"),
678    F13 = (45, "f13"),
679    F14 = (46, "f14"),
680    F15 = (47, "f15"),
681    F16 = (48, "f16"),
682    F17 = (49, "f17"),
683    F18 = (50, "f18"),
684    F19 = (51, "f19"),
685    F20 = (52, "f20"),
686    F21 = (53, "f21"),
687    F22 = (54, "f22"),
688    F23 = (55, "f23"),
689    F24 = (56, "f24"),
690    F25 = (57, "f25"),
691    F26 = (58, "f26"),
692    F27 = (59, "f27"),
693    F28 = (60, "f28"),
694    F29 = (61, "f29"),
695    F30 = (62, "f30"),
696    F31 = (63, "f31"),
697
698    // Alternate Frame Return Column
699    AFRC = (64, "afrc"),
700
701    V0 = (96, "v0"),
702    V1 = (97, "v1"),
703    V2 = (98, "v2"),
704    V3 = (99, "v3"),
705    V4 = (100, "v4"),
706    V5 = (101, "v5"),
707    V6 = (102, "v6"),
708    V7 = (103, "v7"),
709    V8 = (104, "v8"),
710    V9 = (105, "v9"),
711    V10 = (106, "v10"),
712    V11 = (107, "v11"),
713    V12 = (108, "v12"),
714    V13 = (109, "v13"),
715    V14 = (110, "v14"),
716    V15 = (111, "v15"),
717    V16 = (112, "v16"),
718    V17 = (113, "v17"),
719    V18 = (114, "v18"),
720    V19 = (115, "v19"),
721    V20 = (116, "v20"),
722    V21 = (117, "v21"),
723    V22 = (118, "v22"),
724    V23 = (119, "v23"),
725    V24 = (120, "v24"),
726    V25 = (121, "v25"),
727    V26 = (122, "v26"),
728    V27 = (123, "v27"),
729    V28 = (124, "v28"),
730    V29 = (125, "v29"),
731    V30 = (126, "v30"),
732    V31 = (127, "v31"),
733},
734aliases {
735    ZERO = (0, "zero"),
736    RA = (1, "ra"),
737    SP = (2, "sp"),
738    GP = (3, "gp"),
739    TP = (4, "tp"),
740    T0 = (5, "t0"),
741    T1 = (6, "t1"),
742    T2 = (7, "t2"),
743    S0 = (8, "s0"),
744    FP = (8, "fp"),
745    S1 = (9, "s1"),
746    A0 = (10, "a0"),
747    A1 = (11, "a1"),
748    A2 = (12, "a2"),
749    A3 = (13, "a3"),
750    A4 = (14, "a4"),
751    A5 = (15, "a5"),
752    A6 = (16, "a6"),
753    A7 = (17, "a7"),
754    S2 = (18, "s2"),
755    S3 = (19, "s3"),
756    S4 = (20, "s4"),
757    S5 = (21, "s5"),
758    S6 = (22, "s6"),
759    S7 = (23, "s7"),
760    S8 = (24, "s8"),
761    S9 = (25, "s9"),
762    S10 = (26, "s10"),
763    S11 = (27, "s11"),
764    T3 = (28, "t3"),
765    T4 = (29, "t4"),
766    T5 = (30, "t5"),
767    T6 = (31, "t6"),
768
769    FT0 = (32, "ft0"),
770    FT1 = (33, "ft1"),
771    FT2 = (34, "ft2"),
772    FT3 = (35, "ft3"),
773    FT4 = (36, "ft4"),
774    FT5 = (37, "ft5"),
775    FT6 = (38, "ft6"),
776    FT7 = (39, "ft7"),
777    FS0 = (40, "fs0"),
778    FS1 = (41, "fs1"),
779    FA0 = (42, "fa0"),
780    FA1 = (43, "fa1"),
781    FA2 = (44, "fa2"),
782    FA3 = (45, "fa3"),
783    FA4 = (46, "fa4"),
784    FA5 = (47, "fa5"),
785    FA6 = (48, "fa6"),
786    FA7 = (49, "fa7"),
787    FS2 = (50, "fs2"),
788    FS3 = (51, "fs3"),
789    FS4 = (52, "fs4"),
790    FS5 = (53, "fs5"),
791    FS6 = (54, "fs6"),
792    FS7 = (55, "fs7"),
793    FS8 = (56, "fs8"),
794    FS9 = (57, "fs9"),
795    FS10 = (58, "fs10"),
796    FS11 = (59, "fs11"),
797    FT8 = (60, "ft8"),
798    FT9 = (61, "ft9"),
799    FT10 = (62, "ft10"),
800    FT11 = (63, "ft11"),
801});
802
803/// Intel i386 architecture specific definitions.
804///
805/// See section 2.4.2 of the [i386 psABI](https://gitlab.com/x86-psABIs/i386-ABI).
806#[derive(Debug, Clone, Copy)]
807pub struct X86;
808
809registers!(X86, {
810    EAX = (0, "eax"),
811    ECX = (1, "ecx"),
812    EDX = (2, "edx"),
813    EBX = (3, "ebx"),
814    ESP = (4, "esp"),
815    EBP = (5, "ebp"),
816    ESI = (6, "esi"),
817    EDI = (7, "edi"),
818
819    // Return Address register. This is stored in `0(%esp, "")` and is not a physical register.
820    RA = (8, "RA"),
821
822    ST0 = (11, "st0"),
823    ST1 = (12, "st1"),
824    ST2 = (13, "st2"),
825    ST3 = (14, "st3"),
826    ST4 = (15, "st4"),
827    ST5 = (16, "st5"),
828    ST6 = (17, "st6"),
829    ST7 = (18, "st7"),
830
831    XMM0 = (21, "xmm0"),
832    XMM1 = (22, "xmm1"),
833    XMM2 = (23, "xmm2"),
834    XMM3 = (24, "xmm3"),
835    XMM4 = (25, "xmm4"),
836    XMM5 = (26, "xmm5"),
837    XMM6 = (27, "xmm6"),
838    XMM7 = (28, "xmm7"),
839
840    MM0 = (29, "mm0"),
841    MM1 = (30, "mm1"),
842    MM2 = (31, "mm2"),
843    MM3 = (32, "mm3"),
844    MM4 = (33, "mm4"),
845    MM5 = (34, "mm5"),
846    MM6 = (35, "mm6"),
847    MM7 = (36, "mm7"),
848
849    MXCSR = (39, "mxcsr"),
850
851    ES = (40, "es"),
852    CS = (41, "cs"),
853    SS = (42, "ss"),
854    DS = (43, "ds"),
855    FS = (44, "fs"),
856    GS = (45, "gs"),
857
858    TR = (48, "tr"),
859    LDTR = (49, "ldtr"),
860
861    FS_BASE = (93, "fs.base"),
862    GS_BASE = (94, "gs.base"),
863});
864
865/// AMD64 architecture specific definitions.
866///
867/// See section 3.6.2 of the [x86-64 psABI](https://gitlab.com/x86-psABIs/x86-64-ABI).
868#[derive(Debug, Clone, Copy)]
869pub struct X86_64;
870
871registers!(X86_64, {
872    RAX = (0, "rax"),
873    RDX = (1, "rdx"),
874    RCX = (2, "rcx"),
875    RBX = (3, "rbx"),
876    RSI = (4, "rsi"),
877    RDI = (5, "rdi"),
878    RBP = (6, "rbp"),
879    RSP = (7, "rsp"),
880
881    R8 = (8, "r8"),
882    R9 = (9, "r9"),
883    R10 = (10, "r10"),
884    R11 = (11, "r11"),
885    R12 = (12, "r12"),
886    R13 = (13, "r13"),
887    R14 = (14, "r14"),
888    R15 = (15, "r15"),
889
890    // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
891    RA = (16, "RA"),
892
893    XMM0 = (17, "xmm0"),
894    XMM1 = (18, "xmm1"),
895    XMM2 = (19, "xmm2"),
896    XMM3 = (20, "xmm3"),
897    XMM4 = (21, "xmm4"),
898    XMM5 = (22, "xmm5"),
899    XMM6 = (23, "xmm6"),
900    XMM7 = (24, "xmm7"),
901
902    XMM8 = (25, "xmm8"),
903    XMM9 = (26, "xmm9"),
904    XMM10 = (27, "xmm10"),
905    XMM11 = (28, "xmm11"),
906    XMM12 = (29, "xmm12"),
907    XMM13 = (30, "xmm13"),
908    XMM14 = (31, "xmm14"),
909    XMM15 = (32, "xmm15"),
910
911    ST0 = (33, "st0"),
912    ST1 = (34, "st1"),
913    ST2 = (35, "st2"),
914    ST3 = (36, "st3"),
915    ST4 = (37, "st4"),
916    ST5 = (38, "st5"),
917    ST6 = (39, "st6"),
918    ST7 = (40, "st7"),
919
920    MM0 = (41, "mm0"),
921    MM1 = (42, "mm1"),
922    MM2 = (43, "mm2"),
923    MM3 = (44, "mm3"),
924    MM4 = (45, "mm4"),
925    MM5 = (46, "mm5"),
926    MM6 = (47, "mm6"),
927    MM7 = (48, "mm7"),
928
929    RFLAGS = (49, "rFLAGS"),
930    ES = (50, "es"),
931    CS = (51, "cs"),
932    SS = (52, "ss"),
933    DS = (53, "ds"),
934    FS = (54, "fs"),
935    GS = (55, "gs"),
936
937    FS_BASE = (58, "fs.base"),
938    GS_BASE = (59, "gs.base"),
939
940    TR = (62, "tr"),
941    LDTR = (63, "ldtr"),
942    MXCSR = (64, "mxcsr"),
943    FCW = (65, "fcw"),
944    FSW = (66, "fsw"),
945
946    XMM16 = (67, "xmm16"),
947    XMM17 = (68, "xmm17"),
948    XMM18 = (69, "xmm18"),
949    XMM19 = (70, "xmm19"),
950    XMM20 = (71, "xmm20"),
951    XMM21 = (72, "xmm21"),
952    XMM22 = (73, "xmm22"),
953    XMM23 = (74, "xmm23"),
954    XMM24 = (75, "xmm24"),
955    XMM25 = (76, "xmm25"),
956    XMM26 = (77, "xmm26"),
957    XMM27 = (78, "xmm27"),
958    XMM28 = (79, "xmm28"),
959    XMM29 = (80, "xmm29"),
960    XMM30 = (81, "xmm30"),
961    XMM31 = (82, "xmm31"),
962
963    K0 = (118, "k0"),
964    K1 = (119, "k1"),
965    K2 = (120, "k2"),
966    K3 = (121, "k3"),
967    K4 = (122, "k4"),
968    K5 = (123, "k5"),
969    K6 = (124, "k6"),
970    K7 = (125, "k7"),
971
972    R16 = (130, "r16"),
973    R17 = (131, "r17"),
974    R18 = (132, "r18"),
975    R19 = (133, "r19"),
976    R20 = (134, "r20"),
977    R21 = (135, "r21"),
978    R22 = (136, "r22"),
979    R23 = (137, "r23"),
980    R24 = (138, "r24"),
981    R25 = (139, "r25"),
982    R26 = (140, "r26"),
983    R27 = (141, "r27"),
984    R28 = (142, "r28"),
985    R29 = (143, "r29"),
986    R30 = (144, "r30"),
987    R31 = (145, "r31"),
988
989    TMM0 = (146, "tmm0"),
990    TMM1 = (147, "tmm1"),
991    TMM2 = (148, "tmm2"),
992    TMM3 = (149, "tmm3"),
993    TMM4 = (150, "tmm4"),
994    TMM5 = (151, "tmm5"),
995    TMM6 = (152, "tmm6"),
996    TMM7 = (153, "tmm7"),
997    TILECFG = (154, "tilecfg"),
998});
999
1000/// PowerPC 64bit
1001///
1002/// See [64-bit ELF ABI Specification for OpenPOWER Architecture](https://openpowerfoundation.org/specifications/64bitelfabi/).
1003#[derive(Debug, Clone, Copy)]
1004pub struct PowerPc64;
1005
1006registers!(PowerPc64, {
1007    R0 = (0, "r0"),
1008    R1 = (1, "r1"),
1009    R2 = (2, "r2"),
1010    R3 = (3, "r3"),
1011    R4 = (4, "r4"),
1012    R5 = (5, "r5"),
1013    R6 = (6, "r6"),
1014    R7 = (7, "r7"),
1015    R8 = (8, "r8"),
1016    R9 = (9, "r9"),
1017    R10 = (10, "r10"),
1018    R11 = (11, "r11"),
1019    R12 = (12, "r12"),
1020    R13 = (13, "r13"),
1021    R14 = (14, "r14"),
1022    R15 = (15, "r15"),
1023    R16 = (16, "r16"),
1024    R17 = (17, "r17"),
1025    R18 = (18, "r18"),
1026    R19 = (19, "r19"),
1027    R20 = (20, "r20"),
1028    R21 = (21, "r21"),
1029    R22 = (22, "r22"),
1030    R23 = (23, "r23"),
1031    R24 = (24, "r24"),
1032    R25 = (25, "r25"),
1033    R26 = (26, "r26"),
1034    R27 = (27, "r27"),
1035    R28 = (28, "r28"),
1036    R29 = (29, "r29"),
1037    R30 = (30, "r30"),
1038    R31 = (31, "r31"),
1039
1040    F0 = (32, "f0"),
1041    F1 = (33, "f1"),
1042    F2 = (34, "f2"),
1043    F3 = (35, "f3"),
1044    F4 = (36, "f4"),
1045    F5 = (37, "f5"),
1046    F6 = (38, "f6"),
1047    F7 = (39, "f7"),
1048    F8 = (40, "f8"),
1049    F9 = (41, "f9"),
1050    F10 = (42, "f10"),
1051    F11 = (43, "f11"),
1052    F12 = (44, "f12"),
1053    F13 = (45, "f13"),
1054    F14 = (46, "f14"),
1055    F15 = (47, "f15"),
1056    F16 = (48, "f16"),
1057    F17 = (49, "f17"),
1058    F18 = (50, "f18"),
1059    F19 = (51, "f19"),
1060    F20 = (52, "f20"),
1061    F21 = (53, "f21"),
1062    F22 = (54, "f22"),
1063    F23 = (55, "f23"),
1064    F24 = (56, "f24"),
1065    F25 = (57, "f25"),
1066    F26 = (58, "f26"),
1067    F27 = (59, "f27"),
1068    F28 = (60, "f28"),
1069    F29 = (61, "f29"),
1070    F30 = (62, "f30"),
1071    F31 = (63, "f31"),
1072
1073    LR = (65, "lr"),
1074    CTR = (66, "ctr"),
1075
1076    CR0 = (68, "cr0"),
1077    CR1 = (69, "cr1"),
1078    CR2 = (70, "cr2"),
1079    CR3 = (71, "cr3"),
1080    CR4 = (72, "cr4"),
1081    CR5 = (73, "cr5"),
1082    CR6 = (74, "cr6"),
1083    CR7 = (75, "cr7"),
1084    XER = (76, "xer"),
1085
1086    VR0 = (77, "vr0"),
1087    VR1 = (78, "vr1"),
1088    VR2 = (79, "vr2"),
1089    VR3 = (80, "vr3"),
1090    VR4 = (81, "vr4"),
1091    VR5 = (82, "vr5"),
1092    VR6 = (83, "vr6"),
1093    VR7 = (84, "vr7"),
1094    VR8 = (85, "vr8"),
1095    VR9 = (86, "vr9"),
1096    VR10 = (87, "vr10"),
1097    VR11 = (88, "vr11"),
1098    VR12 = (89, "vr12"),
1099    VR13 = (90, "vr13"),
1100    VR14 = (91, "vr14"),
1101    VR15 = (92, "vr15"),
1102    VR16 = (93, "vr16"),
1103    VR17 = (94, "vr17"),
1104    VR18 = (95, "vr18"),
1105    VR19 = (96, "vr19"),
1106    VR20 = (97, "vr20"),
1107    VR21 = (98, "vr21"),
1108    VR22 = (99, "vr22"),
1109    VR23 = (100, "vr23"),
1110    VR24 = (101, "vr24"),
1111    VR25 = (102, "vr25"),
1112    VR26 = (103, "vr26"),
1113    VR27 = (104, "vr27"),
1114    VR28 = (105, "vr28"),
1115    VR29 = (106, "vr29"),
1116    VR30 = (107, "vr30"),
1117    VR31 = (108, "vr31"),
1118
1119    VSCR = (110, "vscr"),
1120    TFHAR = (114, "tfhar"),
1121    TFIAR = (115, "tfiar"),
1122    TEXASR = (116, "texasr"),
1123});
1124
1125#[cfg(test)]
1126mod tests {
1127
1128    #[test]
1129    #[cfg(feature = "std")]
1130    fn test_aarch64_registers() {
1131        use super::*;
1132        use std::collections::HashSet;
1133
1134        let mut names = HashSet::new();
1135        for n in (0..=39).chain(46..=127) {
1136            let name = AArch64::register_name(Register(n))
1137                .unwrap_or_else(|| panic!("Register {} should have a name.", n));
1138            assert!(names.insert(name));
1139        }
1140    }
1141
1142    #[test]
1143    #[cfg(feature = "std")]
1144    fn test_power64_registers() {
1145        use super::*;
1146        use std::collections::HashSet;
1147
1148        let mut names = HashSet::new();
1149        for n in (0..=63).chain(68..=75).chain(77..=108) {
1150            let name = PowerPc64::register_name(Register(n))
1151                .unwrap_or_else(|| panic!("Register {} should have a name.", n));
1152            assert!(names.insert(name));
1153        }
1154    }
1155}
gimli/arch.rs

gimli/
arch.rs
